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Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 14. VSET1 and VSET2 (Write)
BIT NAME
X
VSET11–VSET0
DATA BIT
D15–D12
D11–D0
RESET STATE
X
0000 0000 0000
FUNCTION
Don’t care.
VSET11 is the MSB and VSET0 is the LSB. Data format is straight binary.
Table 15. USRK1 and USRK2 (Write)
BIT NAME
X
K11–K0
DATA BIT
D15–D12
D11–D0
RESET STATE
X
N/A
FUNCTION
Don’t care.
K11 is the MSB and K0 is the LSB. Data format is straight binary.
Set the VALARM1 bit, D5, to 1 to enable ALARM func-
tionality for GATE1 voltage measurements. Set the
VWIN1 bit, D4, to 1 to monitor the GATE1 voltage with
the ALARM comparator in windowing mode. Set VWIN1
to 0 to monitor the GATE1 voltage with the ALARM com-
parator in hysteresis mode. Set the TALARM1 bit, D3, to
1 to enable ALARM functionality for channel 1 tempera-
ture measurements. Set the TWIN1 bit, D2, to 1 to moni-
tor the channel 1 temperature with the ALARM
comparator in windowing mode. Set TWIN1 to 0 to moni-
tor the channel 1 temperature with the ALARM compara-
tor in hysteresis mode. Set the IALARM1 bit, D1, to 1 to
enable ALARM functionality for channel 1 sense voltage
(RCS1+ to RCS1-) measurements. Set the IWIN1 bit, D0,
to 1 to monitor the channel 1 sense voltage with the
ALARM comparator in windowing mode. Set IWIN1 to 0
to monitor the channel 1 sense voltage with the ALARM
comparator in hysteresis mode.
VSET1 and VSET2 (Write)
Write to the channel 1/channel 2 V SET registers to set
the V SET(CODE) code in the V DAC(CODE) equations.
Writing to these registers triggers a V DAC(CODE) calcu-
lation. That code is then loaded into either the channel
1/channel 2 DAC input register or channel 1/channel 2
DAC input and output register, depending on the state
of the LDAC1/LDAC2 bits in the software configuration
register. Set the command byte to 40h to write to the
channel 1 V SET register. Set the command byte to 42h
to write to the channel 2 V SET register. See Table 14.
Bits D15–D12 are don’t care. Bits D11–D0 contain the
straight binary data.
USRK1 and USRK2 (Write)
Write to the channel 1/channel 2 K parameter registers
to set the LUT K [K] code in the V DAC(CODE) equation.
The K parameter register value is loaded into the
V DAC(CODE) equation when the KSRC_-2/KSRC_-1/
KSRC_-0 bits in the software configuration register are
set to 010, 101, 110, or 111. See Table 11b. Use the K
parameter as an index to the KLUT or as a multiplier for
the V DAC(CODE) equation in place of V SET(CODE) by
writing to the software configuration register. See Table
11. Set the command byte to 44h to write to the channel
1 K parameter register. Set the command byte to 46h to
write to the channel 2 K parameter register. See Table
15. Bits D15–D12 are don’t care. Bits D11–D0 contain
the straight binary data.
IPDAC1 and IPDAC2 (Write)
Write to the channel 1/channel 2 DAC input registers to
load the DAC code and bypass a V DAC(CODE) calcula-
tion. Transfer the code written to the DAC input registers
to the channel 1/channel 2 DAC output registers by set-
ting the corresponding DACCH_ bit high in the software
load DAC register. Set the command byte to 48h and
4Ch, respectively, to write to the channel 1/channel 2
DAC input registers. See Table 16. Bits D15–D12 are
don’t care. Bits D11–D0 contain the straight binary data.
Writing to these registers overwrites any previous val-
ues loaded from the V DAC(CODE) calculation.
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